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GS82032AT/Q-180/166/133/100 TQFP, QFP Commercial Temp Industrial Temp Features
* FT pin for user-configurable flow through or pipelined operation * Single Cycle Deselect (SCD) operation * 3.3 V +10%/-5% core power supply * 2.5 V or 3.3 V I/O supply * LBO pin for Linear or Interleaved Burst mode * Internal input resistors on mode pins allow floating mode pins * Default to Interleaved Pipelined mode * Byte Write (BW) and/or Global Write (GW) operation * Common data inputs and data outputs * Clock Control, registered, address, data, and control * Internal self-timed write cycle * Automatic power-down for portable applications * JEDEC standard 100-lead TQFP or QFP package -180 5.5 ns 3.2 ns 155 mA 9.1 ns 8 ns 100 mA -166 6 ns 3.5 ns 140 mA 10 ns 8.5 ns 90 mA -133 7.5 ns 4 ns 115 mA 12 ns 10 ns 80 mA -100 10 ns 5 ns 90 mA 15 ns 12 ns 65 mA
64K x 32 2M Synchronous Burst SRAM
Flow Through/Pipeline Reads
180 MHz-100 MHz 8 ns-12 ns 3.3 V VDD 3.3 V and 2.5 V I/O
The function of the Data Output Register can be controlled by the user via the FT mode pin (Pin 14 in the TQFP). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipelined mode, activating the rising-edge-triggered Data Output Register.
SCD Pipelined Reads
The GS82032A is an SCD (Single Cycle Deselect) pipelined synchronous SRAM. DCD (Dual Cycle Deselect) versions are also available. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.
Pipeline 3-1-1-1 Flow Through 2-1-1-1
tCycle tKQ IDD tCycle tKQ IDD
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.
Functional Description
Applications
The GS82032A is a 2,097,152-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.
Core and Interface Voltages
The GS82032A operates on a 3.3 V power supply and all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuit.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Rev: 1.09 7/2002 1/23 (c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82032AT/Q-180/166/133/100
GS82032A 100-Pin TQFP and QFP Pinout
NC DQC8 DQC7 VDDQ VSS DQC6 DQC5 DQC4 DQC3 VSS VDDQ DQC2 DQC1 FT VDD NC VSS DQD1 DQD2 VDDQ VSS DQD3 DQD4 DQD5 DQD6 VSS VDDQ DQD7 DQD8 NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 64K x 32 10 71 11 Top View 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6 A7 E1 E2 BD BC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A8 A9
NC DQB8 DQB7 VDDQ VSS DQB6 DQB5 DQB4 DQB3 VSS VDDQ DQB2 DQB1 VSS NC VDD ZZ DQA1 DQA2 VDDQ VSS DQA3 DQA4 DQA5 DQA6 VSS VDDQ DQA7 DQA8 NC
Rev: 1.09 7/2002
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
LBO A5 A4 A3 A2 A1 A0 NC NC VSS VDD NC NC A10 A11 A12 A13 A14 A15 NC 2/23 (c) 2000, Giga Semiconductor, Inc.
GS82032AT/Q-180/166/133/100
TQFP Pin Description Pin Location
37, 36 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49 52, 53, 56, 57, 58, 59, 62, 63 68, 69, 72, 73, 74, 75, 78, 79 2, 3, 6, 7, 8, 9, 12, 13 18, 19, 22, 23, 24, 25, 28, 29 16, 38, 39, 42, 43, 66, 50, 51, 80, 1, 30 87 93, 94 95, 96 89 88 98, 92 97 86 83 84, 85 64 14 31 15, 41, 65, 91 5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90 4, 11, 20, 27, 54, 61, 70, 77
Symbol
A0, A1 A2-A15 DQA1-DQA8 DQB1-DQB8 DQC1-DQC8 DQD1-DQD8 NC BW BA, BB BC, BD CK GW E1, E3 E2 G ADV ADSP, ADSC ZZ FT LBO VDD VSS VDDQ
Type
I I
Description
Address field LSBs and Address Counter preset Inputs Address Inputs
I/O
Data Input and Output pins No Connect
I I I I I I I I I I I I I I I I
Byte Write--Writes all enabled bytes; active low Byte Write Enable for DQA, DQB Data I/Os; active low Byte Write Enable for DQC, DQD Data I/Os; active low Clock Input Signal; active high Global Write Enable--Writes all bytes; active low Chip Enable; active low Chip Enable; active high Output Enable; active low Burst address counter advance enable; active low Address Strobe (Processor, Cache Controller); active low Sleep Mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Core power supply I/O and Core Ground Output driver power supply
Rev: 1.09 7/2002
3/23
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82032AT/Q-180/166/133/100
GS82032A Block Diagram
Register
A0-An
D
Q A0 D0 A1 Q0 D1 Q1 Counter Load A0 A1
A
LBO ADV CK ADSC ADSP GW BW BA
Register
Memory Array
Q D Q D
Register
D BB
Q
32 4
32
Register
D BC
Q Q
Register
D
Register
Q
Register
D
D BD
Q
Register
D
Q
E1 E2 E3
Register
D
Q
Register
D
Q
FT G Power Down Control DQx1-DQx8
ZZ
Rev: 1.09 7/2002
4/23
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82032AT/Q-180/166/133/100
Mode Pin Functions Mode Name
Burst Order Control Output Register Control Power Down Control
Pin Name
LBO FT ZZ
State
L H or NC L H or NC L or NC H
Function
Linear Burst Interleaved Burst Flow Through Pipeline Active Standby, IDD = ISB
Note: There are pull-up devices on LBO and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above table.
Burst Counter Sequences
Linear Burst Sequence
A[1:0] 1st address 2nd address 3rd address 4th address 00 01 10 11 A[1:0] 01 10 11 00 A[1:0] 10 11 00 01 A[1:0] 11 00 01 10 1st address 2nd address 3rd address 4th address
Interleaved Burst Sequence
A[1:0] 00 01 10 11 A[1:0] 01 00 11 10 A[1:0] 10 11 00 01 A[1:0] 11 10 01 00
Note: The burst counter wraps to initial state on the 5th clock.
Note: The burst counter wraps to initial state on the 5th clock.
Byte Write Truth Table Function
Read Read Write byte A Write byte B Write byte C Write byte D Write all bytes Write all bytes
GW
H H H H H H H L
BW
H L L L L L L X
BA
X H L H H H L X
BB
X H H L H H L X
BC
X H H H L H L X
BD
X H H H H L L X
Notes
1 1 2, 3 2, 3 2, 3, 4 2, 3, 4 2, 3, 4
Notes: 1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs. 2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes. 3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
Rev: 1.09 7/2002
5/23
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82032AT/Q-180/166/133/100
Synchronous Truth Table Operation
Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst
Address Used
None None None External External External Next Next Next Next Current Current Current Current
State Diagram Key5
X X X R R W CR CR CW CW
E1
H L L L L L X H X H X H X H
E2
X F F T T T X X X X X X X X
ADSP ADSC
X L H L H H H X H X H X H X L X L X L L H H H H H H H H
ADV
X X X X X X L L L L H H H H
W3
X X X X F T F F T T F F T T
DQ4
High-Z High-Z High-Z Q Q D Q Q D D Q Q D D
Notes: 1. X = Don't Care, H = High, L = Low 2. E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1 3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding 4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as "Q" in the Truth Table above). 5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity. 6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. 7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 1.09 7/2002
6/23
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82032AT/Q-180/166/133/100 Simplified State Diagram
X
Deselect W W Simple Synchronous Operation R R
X CW
First Write
R CR
First Read
X CR
Simple Burst Synchronous Operation
W R X Burst Write CR CW
R
Burst Read
X
CR
Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, E3) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and that ADSP is tied high and ADSC is tied low. 3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and assumes ADSP is tied high and ADV is tied low.
Rev: 1.09 7/2002
7/23
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82032AT/Q-180/166/133/100 Simplified State Diagram with G
X
Deselect W W X W CW R R
First Write
R CR
First Read
X CR
CW
W X Burst Write R CR W CW
R X
Burst Read
CW
CR
Notes: 1. The diagram shows supported (tested) synchronous state transitions, plus supported transitions that depend upon the use of G. 2. Use of "Dummy Reads" (Read Cycles with G high) may be used to make the transition from Read cycles to Write cycles without passing through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles. 3. Transitions shown in gray assume G has been pulsed high long enough to turn the RAM's drivers off and for incoming data to meet Data Input Set Up Time.
Rev: 1.09 7/2002
8/23
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82032AT/Q-180/166/133/100
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol
VDD VDDQ VCK VI/O VIN IIN IOUT PD TSTG TBIAS
Description
Voltage on VDD Pins Voltage in VDDQ Pins Voltage on Clock Input Pin Voltage on I/O Pins Voltage on Other Input Pins Input Current on Any Pin Output Current on Any I/O Pin Package Power Dissipation Storage Temperature Temperature Under Bias
Value
-0.5 to 4.6 -0.5 to VDD -0.5 to 6 -0.5 to VDDQ+0.5 ( 4.6 V max.) -0.5 to VDD+0.5 ( 4.6 V max.) +/-20 +/-20 1.5 -55 to 125 -55 to 125
Unit
V V V V V mA mA W
o
C
oC
Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component.
Recommended Operating Conditions Parameter
Supply Voltage I/O Supply Voltage Input High Voltage Input Low Voltage Ambient Temperature (Commercial Range Versions)
Symbol
VDD VDDQ VIH VIL TA
Min.
3.135 2.375 1.7 -0.3 0
Typ.
3.3 2.5 -- -- 25
Max.
3.6 VDD VDD+0.3 0.8 70
Unit
V V V V C
Notes
1 2 2 3
TA Ambient Temperature (Industrial Range Versions) -40 25 85 C 3 Notes: 1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75 V VDDQ 2.375 V (i.e., 2.5 V I/O) and 3.6 V VDDQ 3.135 V (i.e., 3.3 V I/O) and quoted at whichever condition is worst case. 2. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers. 3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of Industrial Temperature Range versions end with the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 4. Input Under/overshoot voltage must be -2 V > Vi < VDD+2 V with a pulse width not to exceed 20% tKC.
Rev: 1.09 7/2002
9/23
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82032AT/Q-180/166/133/100
Undershoot Measurement and Timing
VIH VDD +- 2.0 V VSS 50% VSS - 2.0 V 20% tKC VIL 50% VDD
Overshoot Measurement and Timing
20% tKC
Capacitance
(TA = 25C, f = 1 MHZ, VDD = 3.3 V)
Parameter
Control Input Capacitance Input Capacitance Output Capacitance Note: This parameter is sample tested.
Symbol
CI CIN COUT
Test conditions
VDD = 3.3 V VIN = 0 V VOUT = 0 V
Typ.
3 4 6
Max.
4 5 7
Unit
pF pF pF
Package Thermal Characteristics Rating
Junction to Ambient (at 200 lfm) Junction to Ambient (at 200 lfm)
Layer Board
single four
Symbol
RJA RJA
TQFP Max
40 24
QFP Max
TBD TBD
Unit
C/W C/W
Notes
1,2,4 1,2,4
RJC 9 TBD C/W 3,4 Junction to Case (TOP) Notes: 1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temperature air flow, board density, and PCB thermal resistance. 2. SCMI G-38-87 3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1 4. For x18 configuration, consult factory.
Rev: 1.09 7/2002
10/23
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82032AT/Q-180/166/133/100
AC Test Conditions Parameter
Input high level Input low level Input slew rate Input reference level Output reference level
Conditions
2.3 V 0.2 V 1 V/ns 1.25 V 1.25 V
Output load Fig. 1& 2 Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Output Load 2 for tLZ, tHZ, tOLZ and tOHZ 4. Device is deselected as defined by the Truth Table. Output Load 1 DQ 50 VT = 1.25 V
* Distributed Test Jig Capacitance
Output Load 2 2.5 V 30pF* DQ 5pF* 225 225
DC Electrical Characteristics Parameter
Input Leakage Current (except mode pins) ZZ Input Current Mode Pin Input Current Output Leakage Current Output High Voltage Output High Voltage Output Low Voltage
Symbol
IIL IINZZ IINM IOL VOH VOH VOL
Test Conditions
VIN = 0 to VDD VDD VIN VIH 0V VIN VIH VDD VIN VIL 0V VIN VIL Output Disable, VOUT = 0 to VDD IOH = -4 mA, VDDQ = 2.375 V IOH = -4 mA, VDDQ = 3.135 V IOL = 4 mA
Min
-1 uA -1 uA -1 uA -300 uA -1 uA -1 uA 1.7 V 2.4 V
Max
1 uA 1 uA 300 uA 1 uA 1 uA 1 uA
0.4 V
Rev: 1.09 7/2002
11/23
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82032AT/Q-180/166/133/100
Operating Currents
-180 Parameter Test Conditions Symbol IDD Pipeline IDD Flow Through ISB Flow Through IDD Pipeline IDD Flow Through 0 to 70C 155 100 -40 to 85C 160 105 -166 0 to 70C 140 90 -40 to 85C 145 95 -133 0 to 70C 115 80 -40 to 85C 120 85 -100 0 to 70C 90 65 -40 to 85C 95 70 Unit
Operating Current Standby Current Deselect Current
Device Selected; All other inputs VIH or VIL Output open ZZ VDD - 0.2 V
mA mA
10 35 25
15 40 30
10 30 25
15 35 30
10 30 20
15 35 25
10 25 20
15 30 25
mA mA mA
Device Deselected; All other inputs VIH or VIL
Rev: 1.09 7/2002
12/23
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82032AT/Q-180/166/133/100 AC Electrical Characteristics
Parameter Clock Cycle Time Pipeline Clock to Output Valid Clock to Output Invalid Clock to Output in Low-Z Clock Cycle Time Flow Through Clock to Output Valid Clock to Output Invalid Clock to Output in Low-Z Clock HIGH Time Clock LOW Time Clock to Output in High-Z G to Output Valid G to output in Low-Z G to output in High-Z Setup time Hold time ZZ setup time ZZ hold time ZZ recovery Symbol tKC tKQ tKQX tLZ1 tKC tKQ tKQX tLZ1 tKH tKL tHZ1 tOE tOLZ tS tH tZZS2 tZZH2 tZZR
1
-180 Min 5.5 -- 1.5 1.5 9.1 -- 3 3 1.3 1.5 1.5 -- 0 -- 1.5 0.5 5 1 20 Max -- 3.2 -- -- -- 8 -- -- -- -- 3.2 3.2 -- 3.2 -- -- -- -- -- Min 6 -- 1.5 1.5 10 -- 3 3 1.3 1.5 1.5 -- 0 -- 1.5 0.5 5 1 20
-166 Max -- 3.5 -- -- -- 8.5 -- -- -- -- 3.5 3.5 -- 3.5 -- -- -- -- -- Min 7.5 -- 1.5 1.5 12 -- 3 3 1.3 1.5 1.5 -- 0 -- 1.5 0.5 5 1 20
-133 Max -- 4 -- -- -- 10 -- -- -- -- 4 4 -- 4 -- -- -- -- -- Min 10 -- 1.5 1.5 15 -- 3 3 1.3 1.5 1.5 -- 0 -- 1.5 0.5 5 1 20
-100 Max -- 5 -- -- -- 12 -- -- -- -- 5 5 -- 5 -- -- -- -- --
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tOHZ1
Notes: 1. These parameters are sampled and are not 100% tested. 2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above.
Rev: 1.09 7/2002
13/23
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82032AT/Q-180/166/133/100 Write Cycle Timing
Single Write
Burst Write
Write
Deselected
CK
tS tH
tKH tKL
tKC
ADSP is blocked by E1 inactive
ADSP
tS tH ADSC initiated write
ADSC
tS tH
ADV
tS tH ADV must be inactive for ADSP Write
WR2 WR3
A0-An GW
WR1
tS tH
tS tH
BW
tS tH
BA-BD
tS tH
WR1 WR1
WR2
WR3 WR3
E1 masks ADSP
E1
tS tH Deselected with E2
E2
tS tH E2 and E3 only sampled with ADSP or ADSC
E3 G
tS tH Write specified byte for 2A and all bytes for 2B, 2C& 2D
D2A D2B D2C D2D D3A
DQA-DQD
Hi-Z
D1A
Rev: 1.09 7/2002
14/23
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82032AT/Q-180/166/133/100 Flow Through Read Cycle Timing
Single Read
CK
tS tH tKH tS tH
tKL tKC
Burst Read
ADSP is blocked by E1 inactive
ADSP ADSC
tS tH
ADSC initiated read
Suspend Burst
Suspend Burst
ADV
tS tH
A0-An GW
RD1 tS
RD2
RD3 tH
tS
tH
BW BA-BD
tS tH E1 masks ADSP
E1
tS tH E2 and E3 only sampled with ADSP or ADSC Deselected with E2
E2
tS tH
E3
tOE tOHZ
G
tOLZ tKQX Q1A tLZ tKQ tHZ Q2A Q2B Q2C Q2D Q3A tKQX
DQA-DQD
Hi-Z
Rev: 1.09 7/2002
15/23
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82032AT/Q-180/166/133/100 Flow Through Read-Write Cycle Timing
Single Read Single Write
Burst Read
CK
tS tH tKH tKL tKC ADSP is blocked by E inactive
ADSP
tS tH ADSC initiated read
ADSC
tS tH
ADV
tS tH
A0-An GW
RD1
WR1
RD2
tS tH
tS
tH
BW BA-BD
tS tH tS tH
WR1
E1 masks ADSP
E1
tS tH E2 and E3 only sampled with ADSP and ADSC
E2
tS tH Deselected with E3 tOHZ
E3
tOE
G DQA-DQD
Hi-Z tKQ Q1A
tS
tH Q2A Q2B Q2C Q2D Q2A
D1A
Burst wrap around to it's initial state
Rev: 1.09 7/2002
16/23
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82032AT/Q-180/166/133/100 Pipelined SCD Read Cycle Timing
Single Read Burst Read tKH tKL tKC tS tH ADSP is blocked by E1 inactive
CK
tS tH
ADSP ADSC
tS tH
ADSC initiated read
Suspend Burst
ADV
tS tH
An GW
RD1 tS
RD2
RD3 tH
tS
tH
BW BWA-BWD
tS tH E1 masks ADSP
E1
tS tH E2 and E3 only sampled with ADSP or ADSC Deselected with E2
E2
tS tH
E3
tOE
G DQA-DQD
Hi-Z tOLZ Q1A tLZ tKQ
tOHZ tKQX Q2A Q2B Q2C Q2D
tKQX Q3A tHZ
Rev: 1.09 7/2002
17/23
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82032AT/Q-180/166/133/100 Pipelined SCD Read - Write Cycle Timing
Single Read tKL Single Write Burst Read
CK
tS tH tKH tKC ADSP is blocked by E inactive
ADSP
tS tH ADSC initiated read
ADSC ADV
tS tH
tS tH
A0-An GW
RD1
WR1
RD2
tS tH
tS
tH
BW
tS tH
BA-BWD
tS tH
WR1
E1 masks ADSP
E1
tS tH E2 and E3 only sampled with ADSP and ADSC
E2
tS tH Deselected with E3
E3
tOE tOHZ
G DQA-DQD
Hi-Z tKQ Q1A
tS tH D1A Q2A Q2B Q2C Q2D
Rev: 1.09 7/2002
18/23
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82032AT/Q-180/166/133/100 Sleep Mode Timing Diagram
CK
tS tH tKC tKH tKL
ADSP ADSC
tZZS
~ ~~~~ ~ ~ ~~~~ ~
tZZH
ZZ
tZZR
Snooze
Application Tips
Single and Dual Cycle Deselect
SCD devices force the use of "dummy read cycles" (read cycles that are launched normally, but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention.
Rev: 1.09 7/2002
19/23
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82032AT/Q-180/166/133/100 GS82032A Output Driver Characteristics
60
Pull Down Drivers
40
20 VDDQ I Out 0 I Out (mA) VOut VSS
-20
-40
Pull Up Drivers
-60
-80 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4
V Out (Pull Dow n) VDDQ - V Out (Pull Up) 3.6V PD LD 3.3V PD LD 3.1V PD LD 3.1V PU LD 3.3V PU LD 3.6V PU LD
Rev: 1.09 7/2002
20/23
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82032AT/Q-180/166/133/100 TQFP and QFP Package Drawing
L L1 c Pin 1
e b
D D1
A1
Y
A2
E1 E
Symbol
A1 A2 b c D D1 E E1 e L L1 Y
Description
Standoff Body Thickness Lead Width Lead Thickness Terminal Dimension Package Body Terminal Dimension Package Body Lead Pitch Foot Length Lead Length Coplanarity Lead Angle
Min.
0.05 1.35 0.20 0.09 21.9 19.9 15.9 13.9 -- 0.45 -- -- 0
TQFP Nom.
0.10 1.40 0.30 -- 22.0 20.0 16.0 14.0 0.65 0.60 1.00 -- --
Max
0.15 1.45 0.40 0.20 22.1 20.1 16.1 14.1 -- 0.75 -- 0.10 7
Min.
0.25 2.55 0.20 0.10 22.95 19.9 17.0 13.9 -- .60 -- -- 0
QFP Nom.
0.35 2.72 0.30 0.15 23.2 20.0 17.2 14.0 0.65 0.80 1.60 -- --
Max
0.45 2.90 0.40 0.20 23.45 20.1 17.4 14.1 -- 1.00 -- 0.10 7
Notes: 1. All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion. Rev: 1.09 7/2002 21/23 (c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82032AT/Q-180/166/133/100
Ordering Information for GSI Synchronous Burst RAMs Org
64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32
Part Number1
GS82032AT-180 GS82032AT-166 GS82032AT-133 GS82032AT-4 GS82032AT-5 GS82032AT-6 GS82032AT-180I GS82032AT-166I GS82032AT-133I GS82032AT-4I GS82032AT-5I GS82032AT-6I GS82032AQ-180 GS82032AQ-166 GS82032AQ-133 GS82032AQ-4 GS82032AQ-5 GS82032AQ-6 GS82032AQ-180I GS82032AQ-166I GS82032AQ-133I GS82032AQ-4I GS82032AQ-5I GS82032AQ-6I
Type
Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through
Package
TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP QFP QFP QFP QFP QFP QFP QFP QFP QFP QFP QFP QFP
Speed2 TA (MHz/ns) 3
180/8 166/8.5 133/10 133/10 100/12 100/12 180/8 166/8.5 133/10 133/10 100/12 100/12 180/8 166/8.5 133/10 133/10 100/12 100/12 180/8 166/8.5 133/10 133/10 100/12 100/12 C C C C C C I I I I I I C C C C C C I I I I I I
Status
Notes: 1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS82032AT-100IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.09 7/2002
22/23
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82032AT/Q-180/166/133/100 Revision History
DS/DateRev. Code: Old;
New GS82032 Rev 1.03 2/ 2000D;GS820321.04 3/ 2000E GS820321.04 3/2000E; GS82032A_r1_05
Types of Changes Revisions Format or Content
Content * First Release of A version. Added "A" Version to 82032T/Q, 820E32TQ, and 820H32TQ * Updated ADSC in timing diagrams on pages 16 and 18 * Added 200 MHz, 180 MHz, and 166 MHz speed bins (all references updated) * Deleted 150 MHz, 138 MHz, and 66 MHz speed bins (all references deleted) * Deleted BGA reference in "Flow Through/Pipeline Reads" on page 1 * Updated entire datasheet with new standards * Updated table on page 1 * Updated Operating Currents table on page 12 * Updated Electrical Characteristics table on page 13 * Updated format to comply with Technical Publications standards * Added the following part numbers to the Ordering Information table on page 22: - GS82032AT-4 - GS82032AT-6 - GS82032AT-4I - GS82032AT-6I - GS82032AQ-4 - GS82032AQ-6 - GS82032AQ-4I - GS82032AQ-6I * Removed all references to 200 MHz parts (no longer active)
Content
82032A_r1_05; 82032A_r1_06
Content
82032A_r1_06; 82032A_r1_07
Content
82032A_r1_07; 82032A_r1_08
Content
82032A_r1_08; 82032A_r1_09
Content
Rev: 1.09 7/2002
23/23
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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